Design research of the DES against power analysis attacks based on FPGA

Aiming at the DES design scheme against power analysis attacks introduced by Standart et al., an improved scheme is presented in this paper. In the improved scheme, eight dummy S-Boxes are proposed to make the power consumption of the DES S-Box logic gates constant instead of random, and it can make the same difficulties for power analysis attackers consuming 98% less memories as compared with the previous scheme. By analyzing the improved scheme in theory and using an accurate circuit simulator, the secure efficacy of the improved one is verified. The verification results indicate that the improved scheme can satisfy the practical applications against power analysis attacks, and it can be also introduced into the FPGA implementations of other cryptographic algorithms' S-Box against power analysis attacks. (C) 2010 Elsevier B.V. All rights reserved.