Demonstration of narrow switching distributions in STT-MRAM arrays for LLC applications at 1x nm node

被引：17

作者：

Edwards, E. R. J. ^{[1
]}

Hu, G. ^{[1
]}

Brown, S. L. ^{[1
]}

D'Emic, C. P. ^{[1
]}

Gottwald, M. G. ^{[1
]}

Hashemi, P. ^{[1
]}

Jung, H. ^{[1
]}

Kim, J. ^{[1
]}

Lauer, G. ^{[1
]}

Nowak, J. J. ^{[1
]}

Sun, J. Z. ^{[1
]}

Suwannasiri, T. ^{[1
]}

Trouilloud, P. L. ^{[1
]}

Woo, S. ^{[1
]}

Worledge, D. C. ^{[1
]}

机构：

[1] IBM TJ Watson Res Ctr, IBM Samsung MRAM Alliance, Yorktown Hts, NY 10598 USA

来源：

2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2020年

关键词：

D O I：

10.1109/IEDM13553.2020.9371985

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We demonstrate spin-transfer torque magnetoresistive random access memory (STT-MRAM) arrays achieving 2.8e-10 write error rate (WER) performance at 3 ns write duration at a magnetic tunnel junction (MTJ) diameter of 40 nm. The bit-to-bit distribution of the write voltage at a WER of 1e-6 is characterized by a relative standard deviation of 3.7% for W0 and 4.5% for W1, sufficient to meet the write voltage distribution requirement for last-level cache (LLC) applications at 1x nm nodes.

引用

页数：4