STT-MRAM Architecture with Parallel Accumulator for In-Memory Binary Neural Networks

In this paper, a row-wise XNOR accumulator architecture for STT-MRAM arrays is proposed for parallel and efficient multiply-and-accumulate (MAC) operation. The proposed accumulator supports in-memory computing and binary neural network (BNN) applications. In the proposed architecture, inputs are fed from the complementary bitlines, whereas readout is performed through a time-based sense amplifier (TBS). The proposed architecture that does not require any ADC can exhibit an average error rate of 0.085 for XNOR vector size (i.e., accumulate capacity) of 128 bits, which translates into 98.45% classification accuracy of a multi-layer perceptron (MLP) on the MNIST dataset.