Design of a Highly Robust Triple-Node-Upset Self-Recoverable Latch

Due to semiconductor technology scaling, integrated circuits have become more sensitive to soft errors. To effectively tolerate multi-node-upsets caused by soft errors and reduce the power dissipation and delay of a latch, this paper proposes a novel triple-node-upset (TNU) self-recoverable latch design, namely, a highly robust TNU self-recoverable (HTNURE) latch, with many redundant nodes and cyclic storage based on 32-nm CMOS technology. The proposed latch uses the Muller C-element as a basic module and can recover all nodes after a TNU occurs. It has low power dissipation and delay due to the application of clock gating technology and high-speed transmission path technology. The proposed latch design was verified by simulations, and simulation results validate its advantages of low power and delay, and high robustness. In addition, compared with the state-of-the-art TNU-tolerant latches, the proposed latch reduces power dissipation, transmission delay, and power-delay-product by approximately 52%, 25%, and 34%, respectively, with a roughly 17% increase in the number of transistors. Furthermore, the proposed latch is the most cost-effective compared with the TNU-self-recoverable latches, and has less or equivalent sensitivity to the process, voltage, and temperature variation compared with the reference latches.