Roundoff noise analysis in digital systems for arbitrary sampling rate conversion

被引：1
|
作者：
Evangelista, G [1 ]
机构：
[1] SIEMENS ICM Mobile Phones, D-81667 Munich, Germany
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2003年 / 50卷 / 12期
关键词：
arbitrary sampling rate conversion; efficient digital multirate system; finite signal wordlength; input quantization; multiplication roundoff error; output quantization; quantization noise; roundoff noise;
D O I：
10.1109/TCSII.2003.820251
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this brief, the impact of finite-signal wordlengths on the performance of digital systems for arbitrary sampling rate conversion (ASRC), where input and output sampling rates are derived from independent clock generators, is investigated. For two different efficient realizations of ASRC the noise power due to both, input/output quantization and multiplication roundoff errors, is determined as a function of the signal wordlengths and system parameters, respectively. The obtained system degradation, estimated on basis of the standard model of quantization by rounding, is verified by simulation. As a result, simple design rules for the appropriate selection of the various ASRC-inherent signal wordlengths are given subject to the required system performance.
引用
收藏
页码：1016 / 1023
页数：8
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