High-level synthesis of data paths with concurrent error detection

被引：19

作者：

Antola, A ^{[1
]}

Piuri, V ^{[1
]}

Sami, M ^{[1
]}

机构：

[1] Politecn Milan, Dipartimento Elettron & Informaz, I-20133 Milan, Italy

来源：

1998 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS | 1998年

关键词：

D O I：

10.1109/DFTVS.1998.732178

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

High-level synthesis of data paths with concurrent self-checking abilities is discussed to balance redundancy latency, and checking effectiveness. The nominal and the checking computations are scheduled and allocated contemporaneously by using a force-directed approach to limit the number of redundant units required to achieve detection within the latency of the nominal computation only. Resource sharing between the nominal and the checking computation is used to minimise the redundancy, while keeping error aliasing as reduced as possible.

引用

页码：292 / 300

页数：9

共 11 条

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