Bit Level FIR Filter Optimization using Hybrid Artificial Bee Colony algorithm

Low power and portability (small area) are important issues in digital integrated circuit design. The dynamic power consumption in a circuit depends on hardware complexity and switching activity. Specifically in the subcomponents of digital circuits like FIR filters, power consumption can be directly related to the node switching activity. The more accurate optimization in filter design can be done at bit level. However bit level optimization is quite impractical because of the computational complexity. To control the density of the search space, a two level hybrid optimization approach has been proposed. Word level optimization for filter design has been performed using artificial bee colony algorithm. Thereafter, in the reduced search space Nelder Mead algorithm has been used with bit level objective of reduction in dynamic power consumption.