Two-Dimensions Vernier Time-to-Digital Converter

被引：121

作者：

Vercesi, Luca ^{[1
]}

Liscidini, Antonio ^{[1
]}

Castello, Rinaldo ^{[1
]}

机构：

[1] Univ Pavia, Lab Microelettron, I-27100 Pavia, Italy

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2010年 / 45卷 / 08期

关键词：

All digital PLL; TDC calibration; time to digital converter; Vernier; CMOS; TDC; PLL;

D O I：

10.1109/JSSC.2010.2047435

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A two-dimensions Vernier algorithm applied to a time to digital converter (TDC) is presented. The solution proposed minimizes the length of the delay lines used to perform the digital conversion leading to a better efficiency compared to traditional linear approaches. A 7-bits TDC prototype, targeted for all digital PLL application, was realized in 65 nm CMOS technology with a time resolution of 4.8 ps and a power consumption of 1.65 mW for a conversion rate of 50 Msps. The longest delay line used in such a prototype is one third than what would have been required for a standard Vernier TDC.

引用

页码：1504 / 1512

页数：9

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