A Method of Phase-locked loop Performance Testing

被引：0

作者：

Zhang, Ping ^{[1
]}

Zhang, Jianmin ^{[1
]}

Song, Yanmin ^{[1
]}

Xing, Zuocheng ^{[3
]}

Deng, Qinxue ^{[2
]}

机构：

[1] Tianjin Univ Technol & Educ, Sch Elect Engn, Tianjin, Peoples R China

[2] Xian Siyuan Univ, Comp Sch, Xian, Peoples R China

[3] Natl Univ Def Technol, Comp Sch, Changsha, Peoples R China

来源：

PROCEEDINGS OF THE 2009 2ND INTERNATIONAL CONGRESS ON IMAGE AND SIGNAL PROCESSING, VOLS 1-9 | 2009年

关键词：

Phase-locked loop; performance testing; test logics; hardware overheads;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In general, CPU may upgrade its frequency by the PLL (Phase-locked loop), but the cost of testing is very expensive for high frequency signals. This paper introduces the method that inserts test logics in the CPU to implement its PLL performance testing. It is very easy to implement, and reduces effectively test costs in the case of low hardware overheads. The result shows that the test logics can fulfill the PLL performance testing.

引用

页码：4885 / +

页数：2

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