Failure Triage in RTL Regression Verification

被引:3
作者
Poulos, Zissis [1 ]
Veneris, Andreas [1 ]
机构
[1] Univ Toronto, Elect & Comp Engn Dept, Toronto, ON M5S 1A1, Canada
关键词
Debug; failure triage; register transfer level (RTL); regression verification; satisfiability; DIAGNOSIS;
D O I
10.1109/TCAD.2017.2783303
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We propose an automated failure triage framework for register transfer level debugging in functional verification regression flows which unifies three critical aspects of the problem: the approximation of the general location of root-cause(s) in the design under verification, the binning of all related failures generated by regression runs, and the distribution of these binned failures to the proper engineer(s) for detailed analysis. The proposed triage engine entails two novel methodologies. The first is a classification framework that mines information from SAT-based debugging and simulation to probabilistically reason about the relation of root-causes with their respective failing verification traces. This enables the construction of a priority ranking for these root-causes, and can effectively guide debugging by focusing resources on high-priority root-causes. Second, we propose a formulation of failure binning as exemplar-based clustering for grouping and distributing failing traces to the proper engineering team(s). Experiments on industrial designs show that the proposed methodology achieves 84% and 81 % accuracy when it comes to failure grouping and distribution, respectively, with only a 6.5% runtime overhead over existing debugging state-of-the-art techniques.
引用
收藏
页码:1893 / 1906
页数:14
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