Experimental Demonstration of the High-Performance Floating-Body/Gate DRAM Cell for Embedded Memories

被引:2
作者
Wu, Qingqing [1 ,2 ]
Chen, Jing [1 ]
Lu, Zhichao [3 ]
Zhou, Zhenming [3 ]
Luo, Jiexin [1 ,2 ]
Chai, Zhan [1 ]
Yu, Tao [1 ]
Qiu, Chao [1 ,2 ]
Li, Le [4 ]
Pang, Albert [4 ]
Wang, Xi [1 ]
Fossum, Jerry G. [3 ]
机构
[1] Chinese Acad Sci, Shanghai Inst Microsyst & Informat Technol, State Key Lab Funct Mat Informat, Shanghai 200050, Peoples R China
[2] Chinese Acad Sci, Grad Univ, Beijing 100049, Peoples R China
[3] Univ Florida, Dept Elect & Comp Engn, Gainesville, FL 32611 USA
[4] Grace Semicond Mfg Corp, Shanghai 201203, Peoples R China
关键词
Capacitorless DRAM; overlap; SOI floating-body cell (FBC); tunneling field-effect transistor (T-FET); underlap;
D O I
10.1109/LED.2012.2190031
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A capacitorless DRAM cell, floating-body/gate cell (FBGC), is experimentally presented with planar partially depleted SOI CMOS technology. The specially designed gate/drain underlap and gate/source overlap of the first transistor enable long worst case retention time as well as the fast write speed. The operation power dissipation is dramatically reduced while maintaining high sense margin. In addition, FBGC demonstrates excellent endurance performance and nondestructive read operation.
引用
收藏
页码:743 / 745
页数:3
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