Improved Synthesis of Compressor Trees on FPGAs in High-level Synthesis

被引：2

作者：

Tu, Le ^{[1
]}

Yuan, Yuelai ^{[1
]}

Huang, Kan ^{[1
]}

Zhang, Xiaoqiang ^{[1
]}

Wang, Zixin ^{[1
]}

Chen, Dihu ^{[1
]}

机构：

[1] Sun Yat Sen Univ, Sch Elect & Informat Technol, Guangzhou, Guangdong, Peoples R China

来源：

2017 IEEE 25TH ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM 2017) | 2017年

关键词：

compressor tree synthesis; high-level synthesis;

D O I：

10.1109/FCCM.2017.11

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, an approach to synthesize compressor trees in High-level Synthesis (HLS) for FPGAs is proposed. Our approach utilizes the bit-level information to improve the compressor tree synthesis. To obtain the bit-level information targeting compressor tree synthesis, a modified bitmask analysis technique based on prior work is proposed. A series of experimental results show that, compared to the existing heuristic, the average reductions of area and delay are 22.96% and 7.05%. The reductions increase to 29.97% and 9.07% respectively, when the carry chains in FPGAs are utilized to implement the compressor trees.

引用

页码：25 / 25

页数：1

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