Nonlinear characteristics and RF losses of CPW and TFMS lines over a wide temperature range

被引:0
作者
Ben Ali, K. [1 ]
Raskin, J. -P. [1 ]
机构
[1] Catholic Univ Louvain, B-1348 Louvain La Neuve, Belgium
来源
2016 IEEE 16TH TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS (SIRF) | 2016年
关键词
CPW; TFMS; HR-SOI; RF losses; non-linearity; high temperature; SOI SUBSTRATE; TECHNOLOGY; CMOS;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper analyzes RF losses and non-linear behavior from room temperature up to 175 degrees C of coplanar waveguide (CPW) and thin film microstrip (TFMS) lines fabricated on both High Resistivity (HR) and Standard resistivity (STD) Silicon-on-Insulator (SOI) substrates. Through measurements it is shown that CPW topology exhibits larger 2nd harmonic distortion level, more than 25 dB higher compared with TFMS counterpart at 25 degrees C, whereas the later shows larger insertion losses. At higher temperature, RF losses increase for both transmission line topologies whereas the 2nd and 3rd harmonic levels are almost not affected by the temperature increase.
引用
收藏
页码:24 / 26
页数:3
相关论文
共 10 条
[1]  
Ali K. B., 2012, P IEEE INT SOI C NAP, P112
[2]   RF Performance of SOI CMOS Technology on Commercial 200-mm Enhanced Signal Integrity High Resistivity SOI Substrate [J].
Ben Ali, Khaled ;
Neve, Cesar Roda ;
Gharsallah, Ali ;
Raskin, Jean-Pierre .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (03) :722-728
[3]   Ultrawide Frequency Range Crosstalk Into Standard and Trap-Rich High Resistivity Silicon Substrates [J].
Ben Ali, Khaled ;
Neve, Cesar Roda ;
Gharsallah, Ali ;
Raskin, Jean-Pierre .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2011, 58 (12) :4258-4264
[4]   RF CMOS on high-resistivity substrates for system-on-chip applications [J].
Benaissa, K ;
Yang, JY ;
Crenshaw, D ;
Williams, B ;
Sridhar, S ;
Ai, J ;
Boselli, G ;
Zhao, S ;
Tang, SP ;
Ashburn, S ;
Madhani, P ;
Blythe, T ;
Mahalingam, N ;
Shichijo, H .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (03) :567-576
[5]  
Desbonnets E., 2015, RF SOI WAFER CHARACT
[6]   Behaviour of TFMS and CPW line on SOI substrate versus high temperature for RF applications [J].
Moussa, M. Si ;
Pavageau, C. ;
Lederer, D. ;
Picheta, L. ;
Danneville, F. ;
Fel, N. ;
Russat, J. ;
Raskin, J. -P. ;
Vanhoenacker-Janvier, D. .
SOLID-STATE ELECTRONICS, 2006, 50 (11-12) :1822-1827
[7]   RF Harmonic Distortion of CPW Lines on HR-Si and Trap-Rich HR-Si Substrates [J].
Neve, Cesar Roda ;
Raskin, Jean-Pierre .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2012, 59 (04) :924-932
[8]  
NEVE CR, 2008, 38 EUROPEAN MICROWAV, P36
[9]   Substrate crosstalk reduction using SOI technology [J].
Raskin, JP ;
Viviani, A ;
Flandre, D ;
Colinge, JP .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1997, 44 (12) :2252-2261
[10]   COPLANAR WAVE-GUIDES AND MICROWAVE INDUCTORS ON SILICON SUBSTRATES [J].
REYES, AC ;
ELGHAZALY, SM ;
DORN, SJ ;
DYDYK, M ;
SCHRODER, DK ;
PATTERSON, H .
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 1995, 43 (09) :2016-2022