Dislocation-free relaxed SiGe-on-insulator mesa structures fabricated by high-temperature oxidation

Relaxed SiGe-on-Insulator (SGOI) mesa structures were fabricated using mesa etching and successive high-temperature oxidation of SiGe layer on a Si-on-insulator (SOI) substrate for strained SOI (SSOI) metal-oxide-semiconductor field effect transistors (MOSFETs). In this procedure, the oxidation induces an increase in Ge fraction in the SiGe layer due to the rejection of Ge atoms from the oxide layer, while the mesa isolation enhances the lattice relaxation in the SiGe mesa. As a consequence, almost fully relaxed SGOI mesa structures with the Ge fraction up to 0.35 were obtained without introducing dislocations and surface undulation. Raman measurements revealed that a higher relaxation has been obtained for smaller and thicker mesas as well as at higher oxidation temperature. The experimental results were qualitatively explained by a relaxation model in which a strained SiGe island expands laterally without introducing dislocations on a plastic substrate. Based on this model, the applicability of this method to the fabrication of scaled MOSFETs was examined. In conclusion, this technique is promising for the fabrication of dislocation-free SGOI layers for scaled SSOI-MOSFETs without using any processes which are incompatible with conventional MOSFET processes. (C) 2003 American Institute of Physics.