2:1 Multiplexer Based Design for Ternary Logic Circuits

This paper presents a design methodology using multiplexers to implement any ternary logic function with carbon nanotube field effect transistors ( CNFETs). Ternary logic is one of the promising alternatives to conventional binary logic, since it is possible to achieve simplicity and low power dissipation due to the reduced circuit such as interconnects and chip area. The paper presents a design methodology which uses the combination of Binary 2:1 multiplexers and Ternary multiplexers, to implement Ternary logic circuits. A 1- bit half adder circuits is implemented using the proposed methodology. The proposed implementations are compared with the existing designs for parameters like delay, power etc. Two kinds of 1-bit half adders i.e., delay optimized and power optimized half adders have been designed. Simulation results indicate that the proposed multiplexer based 1-bit half adder design results in 58% average power reduction and 64% power delay product reduction when compared to the existing multiplexer based design.