Rigorous Electrical Modeling of Through Silicon Vias (TSVs) with MOS Capacitance Effects

被引：77

作者：

Bandyopadhyay, Tapobrata ^{[1
]}

Han, Ki Jin ^{[2
]}

Chung, Daehyun ^{[3
]}

Chatterjee, Ritwik ^{[4
]}

Swaminathan, Madhavan ^{[5
]}

Tummala, Rao ^{[1
]}

机构：

[1] Georgia Inst Technol, Microsyst Packaging Res Ctr, Atlanta, GA 30332 USA

[2] IBM TJ Watson Res Ctr, Yorktown Hts, NY 10598 USA

[3] NVIDIA Corp, Santa Clara, CA 95050 USA

[4] McGarry Bair PC, Grand Rapids, MI 49503 USA

[5] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA

来源：

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY | 2011年 / 1卷 / 06期

关键词：

3-D integration; interconnection modeling; parametric study; power distribution network; through silicon via; variable capacitance; THROUGH-WAFER INTERCONNECTS; OPPORTUNITIES; PERFORMANCE; TECHNOLOGY; IMPACT;

D O I：

10.1109/TCPMT.2011.2120607

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

3-D integration of microelectronic systems reduces the interconnect length, wiring delay, and system size, while enhancing functionality by heterogeneous integration. Through silicon via (TSV) is a key building block for high-performance 3-D systems. This paper presents an accurate electrical modeling of TSVs considering metal-oxide-semiconductor (MOS) capacitance effects. The model is correlated with measurement results for validation. Parametric analysis of TSV capacitance is performed on several physical and material parameters. Design guidelines are proposed for TSVs used in signal and power distribution networks as well as for TSVs as variable capacitors. A 3-D power distribution network is simulated to show the effect and importance of the voltage-dependent TSV MOS capacitance.

引用

页码：893 / 903

页数：11

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