Memory Reliability Estimation Degraded by TDDB Using Circuit-Level Accelerated Life Test

As memory technology scales down, memory cells tend to become unreliable. To guarantee reliable operations of circuits and systems, semiconductor devices are tested with accelerated life tests to estimate device-level reliability and to develop a predictive reliability model for circuits and systems based on the estimated reliability of devices. However, to accurately estimate the lifetime of a system, accelerated lifetime testing at the system level is necessary. In this paper, we propose a system-level accelerated life test plan. As a case study, we investigate the reliability of SRAMs under time-dependent dielectric breakdown, one of the major contributors to aging failures in modern computer systems. Using the simulation results, we examine failure trends at various stress conditions for the system-level accelerated life test. From the resulting observations, we suggest a method that optimizes the experimental design of system-level accelerated life tests.