A 1.5-V 12-bit power-efficient continuous-time third-order ΣΔ modulator

This paper presents the design strategy, implementation, and experimental results of a power-efficient third-order low-pass Sigma Delta analog-to-digital converter (ADC) using a continuous-time (CT) loop filter. The loop filter has been implemented by using active RC integrators. Several power optimizations, design requirements, and performance limitations relating to circuit nonidealities; in the CT modulator are Presented. the influence of the low supply voltage on the various building blocks such as the amplifier as well as on the overall Sigma Delta modulator is discussed. The ADC was implemented in a 3.3-V 0.5-mum CMOS technology with standard threshold voltages. Measurements of the low-power 1.5-V CT E A ADC show a dynamic range and peak signal-to-noise-plus- distortion ratio of 90 and 70 dB, respectively, in a bandwidth of 25 kHz. The measured power consumption is only 135 muW from a single 1.5-V power'supply.