A review of the top of the barrier nanotransistor models for semiconductor nanomaterials

The modelling and simulation of low-dimensional nanoelectronic devices is important, because the semiconductor industry has scaled transistors down to the sub-10 nm regime. The top of the barrier (ToB) transistor model has been developed and used to model transistors that are composed of various semiconducting materials. In this paper, a brief overview of the ToB transistor model is presented. The main objective of this paper is to provide a focused review on the device modelling milestones that have been achieved using the ToB transistor model. The accuracy of a few of these models is assessed by computing the normalised root mean square deviation. The ToB transistor model is widely used for computational studies on low-dimensional field-effect transistors with various channel materials, such as ultra-thin-bodies, two-dimensional materials and one-dimensional materials. The ToB transistor model is also useful for extensive research in circuit-level simulations. In summary, this nanoscale model helps researchers to identify and evaluate the potential nanomaterials for future nanoelectronic applications.