共 51 条
[1]
[Anonymous], 2020, METROLOGY, V2020
[2]
Towards 3nm overlay and critical dimension uniformity: an integrated error budget for double patterning lithography - art. no. 692404
[J].
OPTICAL MICROLITHOGRAPHY XXI, PTS 1-3,
2008, 6924
:92404-92404
[3]
Bourcier F., 2020, U.S. Patent, Patent No. [16,028,695, 16028695]
[4]
Determination of optimal parameters for CD-SEM measurement of line edge roughness
[J].
METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XVIII, PTS 1 AND 2,
2004, 5375
:515-533
[5]
7/5 nm Logic Manufacturing Capabilities and Requirements of Metrology
[J].
METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XXXII,
2018, 10585
[6]
Chen Y.D, 2019, ADV PATTERNING TECHN
[7]
Cho D., 2021, PROC SPIE, V11611, DOI [10.1117/12.2584200, DOI 10.1117/12.2584200]
[9]
Stochastic effects in EUV lithography: random, local CD variability, and printing failures
[J].
JOURNAL OF MICRO-NANOLITHOGRAPHY MEMS AND MOEMS,
2017, 16 (04)
[10]
Scatterometry for advanced process control in semiconductor device manufacturing
[J].
FIFTH INTERNATIONAL CONFERENCE ON OPTICAL AND PHOTONICS ENGINEERING,
2017, 10449