Injection-Locked Ring Oscillator based Phase-Locked-Loop for 1.6 Gbps Clock Recovery

This paper submits a proof of concept of an injection-locked Phase-Locked-Loop (PLL) in 180 nm CMOS technology. The target data rate is 1.6 Gbps with a supply voltage of 1.8 V. The architecture is based on an injection-locked ring oscillator implemented in a PLL that helps improving the oscillator jitter and thus the phase noise. In addition, a fully symmetrical XOR gate as phase detector allows to get a low phase noise while simplifying the design. This circuit achieves a phase noise of -119.1 dBc/Hz at 1 MHz and a jitter of 0.6 mUI with a reference frequency of 1.6 GHz. Post-layout simulation results show a PLL locking time with injection at 1.6 GHz of 20 ns while consuming 41.4 mW.