Collective Die-to-Wafer Self-Assembly for High Alignment Accuracy and High Throughput 3D Integration

被引:10
|
作者
Bond, Alice [1 ]
Bourjot, Emilie [1 ]
Borel, Stephan [1 ]
Enot, Thierry [1 ]
Montmeat, Pierre [1 ]
Sanchez, Loic [1 ]
Fournel, Frank [1 ]
Swan, Johanna [2 ]
机构
[1] Univ Grenoble Alpes, CEA LETI, F-38000 Grenoble, France
[2] Intel Corp, 5000 W Chandler Blvd, Chandler, AZ 85226 USA
来源
IEEE 72ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2022) | 2022年
关键词
3D integration; Die-To-Wafer stacking; self-assembly; direct bonding;
D O I
10.1109/ECTC51906.2022.00037
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The die-to wafer hybrid bonding process is considered by leading microelectronics companies as essential for the success of future memory, HPC or photonic devices. However, this process is much more complex than Wafer-To-Wafer bonding and the die assembly throughput is lower. CEA-LETI has been working for several years on the development of a self-assembly process. This latter is promising to increase throughput by self-aligning several thousand of dies per hour. The present paper describes our latest work on self-assembly through a collaboration with Intel, focused on the development and maturation of a collective D2W direct bonding self-assembly process. The water dispense technique and the surface preparation to tune the surface hydrophilicity appeared as critical for the proper conduct of the self-assembly process. Thus, excellent alignment performances on a homemade collective self-assembly bonding bench was achieved. It resulted in a mean misalignment inferior to 150 nm with a 3 sigma inferior to 500 nm. Finally, the compatibility of the self-assembly process with a wide range of die dimensions (8x8 mmz, 2.7x2.7 mm(2), 1.3x11.8 mm(2) and 2.2x11.8 mm(2)) was demonstrated.
引用
收藏
页码:168 / 176
页数:9
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