TSV Manufacturing Yield and Hidden Costs for 3D IC Integration

被引：105
作者：
Lau, John H. [1 ]
机构：
[1] Ind Technol Res Inst, Elect & Optoelect Labs, Hsinchu 310, Taiwan
来源：
2010 PROCEEDINGS 60TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) | 2010年
关键词：
THROUGH-SILICON VIAS; FILLED TSV; WAFER; INTERPOSER; SYSTEM; FABRICATION; TECHNOLOGY; DESIGN;
D O I：
10.1109/ECTC.2010.5490828
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They are different and in general, the TSV (through-silicon-via) separates the 3D IC packaging and 3D IC/Si integrations, i.e., the latter two use TSV, but 3D IC packaging does not. TSV for 3D integration is >26 years old technology, which (with a new concept that every chip could have two active surfaces) is the focus of this study. Emphasis is placed on the TSV manufacturing yield and hidden costs. A 3D integration roadmap is also provided.
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收藏
页码：1031 / 1042
页数：12
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