Short-Channel Performance Improvement by Raised Source/Drain Extensions With Thin Spacers in Trigate Silicon Nanowire MOSFETs

被引：35

作者：

Saitoh, Masumi ^{[1
]}

Nakabayashi, Yukio ^{[1
]}

Uchida, Ken ^{[2
]}

Numata, Toshinori ^{[1
]}

机构：

[1] Toshiba Co Ltd, Corp R&D Ctr, Adv LSI Technol Lab, Yokohama, Kanagawa 2358522, Japan

[2] Tokyo Inst Technol, Tokyo 1528552, Japan

来源：

IEEE ELECTRON DEVICE LETTERS | 2011年 / 32卷 / 03期

关键词：

Drain-induced barrier lowering (DIBL); nanowire transistor; parasitic capacitance; parasitic resistance; raised source/drain (S/D); trigate; TECHNOLOGY; RESISTANCE; SI;

D O I：

10.1109/LED.2010.2101043

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We investigate the short-channel performance of trigate silicon nanowire transistors. Drain-induced barrier lowering at a gate length of 25 nm is strongly suppressed by reducing the nanowire width (W-NW) down to 10 nm. We found that the parasitic resistance (R-SD) of nanowire transistors is dominated by nanowire-shaped source/drain (S/D) regions under the gate spacer whose resistivity is higher than that in wider regions. We succeeded in significant R-SD reduction by raised S/D with thin gate spacer whose width is 10 nm. Although the parasitic capacitance (C-para) increases by spacer thinning, C-para increase is much smaller than R-SD reduction, and great performance improvement is obtained for a W-NW of less than 15 nm.

引用

页码：273 / 275

页数：3