Low-power and High-speed Current-mode CMOS Imager with 1T Biasing Scheme

A low-power and high-speed current-mode CMOS image sensor is proposed in this paper. Only one column-level transistor is used in the read-out circuit as a current conveyor to bias the in-pixel transistor operating in triode region. As a result, the current-mode read-out circuit is significantly simplified by the proposed structure, while saving the power by more than half. The proposed scheme enables less than 20ns output settling time due to very low impedance at the internal high capacitance bus, leading to fast operating speed. In addition, a relevant CDS technique is also proposed in order to reduce the first order coefficient variation. A test structure is fabricated using a CMOS 0.35 mu m. process.