Advanced surface cleaning strategy for 65nm CMOS device performance enhancement

被引：3

作者：

Arnaud, F

Bernard, H

Beverina, A

El-Farhane, R

Duriez, B

Barla, K

Levy, D

机构：

[1] STMicroelect, F-38920 Crolles, France

[2] Philips Semicond, F-38920 Crolles, France

来源：

ULTRA CLEAN PROCESSING OF SILICON SURFACES VII | 2005年 / 103-104卷

关键词：

dopant consumption; low temperature cleaning; CMOS device performance;

D O I：

10.4028/www.scientific.net/SSP.103-104.37

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

This paper investigates low temperature cleaning steps solutions (T degrees < 30 degrees) developed to enhance the 65 nm transistor performance. A complete cleaning recipes optimization is realized in term of silicon consumption and defectiveness for pre-furnace clean (RCA or HFRCA), post gate etch clean PGEC (HF-SPM-SC1) and post ash clean PAC (SPM-SC1) operations. The silicon recess and the dopants consumption are reduced by using low temperature SC1 steps. Transistor drivability is improved by 8% and 7% for NMOS and PMOS respectively.

引用

页码：37 / 40

页数：4