A self-calibration technique for time-interleaved pipeline ADCs

被引：0
|
作者：
Hakkarainen, V [1 ]
Sumanen, L [1 ]
Aho, M [1 ]
Waltari, M [1 ]
Halonen, K [1 ]
机构：
[1] Aalto Univ, Elect Circuit Design Lab, FIN-02015 Espoo, Finland
来源：
PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I: ANALOG CIRCUITS AND SIGNAL PROCESSING | 2003年
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D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, an effective digital self-calibration method for time-interleaved parallel pipeline ADCs is presented. The method corrects errors of MDACs within the channel ADCs and compensates gain and offset mismatches between parallel channels. According to simulations, 14-bit accuracy can be achieved with 10-bit device matching.
引用
收藏
页码：825 / 828
页数：4
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