Digital calibration incorporating redundancy of flash ADCs

被引：49

作者：

Flynn, MP ^{[1
]}

Donovan, C

Sattler, L

机构：

[1] Univ Michigan, Dept Elect Engn & Comp Sci, Ann Arbor, MI 48109 USA

[2] Natl Univ Ireland Univ Coll Cork, Dept Microelect, Cork, Ireland

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2003年 / 50卷 / 05期

基金：

美国国家科学基金会;

关键词：

analog-to-digital conversion; analog redundancy; calibration; flash;

D O I：

10.1109/TCSII.2003.811435

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

As feature size and supply voltage shrink, digital calibration incorporating redundancy of flash analog-to-digital converters is becoming attractive. This new scheme allows accuracy to be achieved through the use of redundancy and reassignment, effectively decoupling analog performance from component matching. Very large comparator offsets (several LSBs) are tolerated, allowing the comparators to be small, fast and. power efficient. In this paper, we analyze this scheme and compare with it with more traditional approaches.

引用

页码：205 / 213

页数：9

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