Proteus: An ASIC Flow for GHz Asynchronous Designs

被引：53

作者：

Beerel, Peter A. ^{[1
]}

Dimou, Georgios D. ^{[1
]}

Lines, Andrew M. ^{[1
]}

机构：

[1] Univ So Calif, Dept Elect Engn Syst, Los Angeles, CA 90089 USA

来源：

IEEE DESIGN & TEST OF COMPUTERS | 2011年 / 28卷 / 05期

关键词：

asynchronous design; asynchronous place and route; communicating sequential processes; design and test; high performance; slack matching;

D O I：

10.1109/MDT.2011.114

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Editors' note:The high-performance benefits of asynchronous design have hitherto been obtained only using full-custom design. This article presents an industrial-strength asynchronous ASIC CAD flow that enables the automatic synthesis and physical design of high-level specifications into GHz silicon, greatly reducing design time and enabling far wider use of asynchronous technology. © 2011 IEEE.

引用

页码：36 / 50

页数：15

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