Cascaded PLL design for a 90nm CMOS high performance microprocessor

被引：0
|
作者：
Wong, KL [1 ]
Fayneh, E [1 ]
Knoll, E [1 ]
Law, RH [1 ]
Lim, CH [1 ]
Parker, RJ [1 ]
Wang, F [1 ]
Zhao, C [1 ]
机构：
[1] Intel, Hillsboro, OR USA
来源：
2003 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE: DIGEST OF TECHNICAL PAPERS | 2003年 / 46卷
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D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：422 / +
页数：3
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