A Versatile Emulator for the Aging Effect of Non-Volatile Memories: The case of NAND Flash

被引：4

作者：

Prodromakis, Antonios ^{[1
]}

Korkotsides, Stelios ^{[1
]}

Antonakopoulos, Theodore ^{[1
]}

机构：

[1] Univ Patras, Dept Elect & Comp Engn, Patras 26504, Greece

来源：

2014 17TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD) | 2014年

关键词：

Non-volatile memories; NAND Flash; Phase Change Memory; Memory Aging; FPGA emulator; RELIABILITY;

D O I：

10.1109/DSD.2014.56

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This work presents a versatile and flexible FPGA-based platform, designed for accurate emulation of the aging effect of non-volatile memories. The emulator is based on a reconfigurable hardware-software architecture which enables the accurate representation of various non-volatile memory technologies, like NAND Flash and PCM. The proposed architecture can be used for emulating memories at the cell, chip and system level, while the proposed hardware platform can be used as a valuable tool for the development and evaluation of memory-related algorithms and techniques. In this paper, we analyze the architecture of the non-volatile memory emulator, focusing mainly on the NAND Flash case, we present details about its internal functionality and, using experimental results, we demonstrate the high accuracy achieved when it is used to emulate a specific NAND Flash chip.

引用

页码：9 / 15

页数：7

共 20 条

[1]

[Anonymous], 2008, OP NAND FLASH INT SP

[2]

Atwood G., 1997, Intel Technology Journal

[3] Introduction to Flash memory [J].

Bez, R ;

Camerlenghi, E ;

Modelli, A ;

Visconti, A .

PROCEEDINGS OF THE IEEE, 2003, 91 (04) :489-502

[4] A NOTE ON THE GENERATION OF RANDOM NORMAL DEVIATES [J].

BOX, GEP ;

MULLER, ME .

ANNALS OF MATHEMATICAL STATISTICS, 1958, 29 (02) :610-611

[5]

Brewer J., 2011, NONVOLATILE MEMORY T, V8

[6]

Cai Y, 2013, DES AUT TEST EUROPE, P1285

[7] ERROR CORRECTION FOR MULTI-LEVEL NAND FLASH MEMORY USING REED-SOLOMON CODES [J].

Chen, Bainan ;

Zhang, Xinmiao ;

Wang, Zhongfeng .

2008 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS: SIPS 2008, PROCEEDINGS, 2008, :94-+

[8] A 19 nm 112.8 mm2 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface [J].

Kanda, Kazushige ;

Shibata, Noboru ;

Hisada, Toshiki ;

Isobe, Katsuaki ;

Sato, Manabu ;

Shimizu, Yui ;

Shimizu, Takahiro ;

Sugimoto, Takahiro ;

Kobayashi, Tomohiro ;

Kanagawa, Naoaki ;

Kajitani, Yasuyuki ;

Ogawa, Takeshi ;

Iwasa, Kiyoaki ;

Kojima, Masatsugu ;

Suzuki, Toshihiro ;

Suzuki, Yuya ;

Sakai, Shintaro ;

Fujimura, Tomofumi ;

Utsunomiya, Yuko ;

Hashimoto, Toshifumi ;

Kobayashi, Naoki ;

Matsumoto, Yuuki ;

Inoue, Satoshi ;

Suzuki, Yoshinao ;

Honda, Yasuhiko ;

Kato, Yosuke ;

Zaitsu, Shingo ;

Chibvongodze, Hardwell ;

Watanabe, Mitsuyuki ;

Ding, Hong ;

Ookuma, Naoki ;

Yamashita, Ryuji .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2013, 48 (01) :159-167

[9]

Korkotsides S., 2014, 6 INT S COMM CONTR S

[10] Estimation of NAND Flash Memory Threshold Voltage Distribution for Optimum Soft-Decision Error Correction [J].

Lee, Dong-hwan ;

Sung, Wonyong .

IEEE TRANSACTIONS ON SIGNAL PROCESSING, 2013, 61 (02) :440-449

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