Test set compaction algorithms for combinational circuits

被引：244

作者：

Hamzaoglu, I ^{[1
]}

Patel, JH ^{[1
]}

机构：

[1] Univ Illinois, Ctr Reliable & High Performance Comp, Urbana, IL 61801 USA

来源：

1998 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN: DIGEST OF TECHNICAL PAPERS | 1998年

关键词：

D O I：

10.1109/ICCAD.1998.742885

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents two new algorithms, Redundant Vector Elimination (RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under the single stuck at fault model, and a new heuristic for estimating the minimum single stuck at fault test set size. These algorithms together with the dynamic compaction algorithm are incorporated into an advanced ATPG system for combinational circuits, called MinTest. MinTest found better lower bounds and generated smaller test sets than the previously published results for the ISCAS85 and full scan version of the ISCAS89 benchmark circuits.

引用

页码：283 / 289

页数：7