Ultra-thin gate dielectric reliability projections

被引：1

作者：

Moosa, M ^{[1
]}

Haggag, A ^{[1
]}

Liu, N ^{[1
]}

Kalpat, S ^{[1
]}

Kuffler, M ^{[1
]}

Menke, D ^{[1
]}

Abramowitz, P ^{[1
]}

Ramón, ME ^{[1
]}

Tseng, HH ^{[1
]}

Luo, TY ^{[1
]}

Lim, S ^{[1
]}

Grudowski, P ^{[1
]}

Jiang, J ^{[1
]}

Min, BW ^{[1
]}

Weintraub, C ^{[1
]}

Chen, J ^{[1
]}

Wong, S ^{[1
]}

Paquette, C ^{[1
]}

Anderson, G ^{[1
]}

Tobin, PJ ^{[1
]}

White, BE ^{[1
]}

Mendicino, M ^{[1
]}

机构：

[1] Freescale Semicond Inc, Austin, TX 78721 USA

来源：

2005 INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY | 2005年

关键词：

D O I：

10.1109/ICICDT.2005.1502609

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Phenomenological time-dependent dielectric breakdown (TDDB) and bias-temperature instability (BTI) models are demonstrated to enable reasonably accurate reliability projections for several generations of silicon oxynitride-based transistors and circuits with EOT down to similar to 1.3nm. Furthermore, while reliability and performance can be traded-off by engineering the gate dielectric coupled with device integration, benchmarking of published data suggests that the reliability achievable at each transistor node falls within an intrinsically plausible range for similar dielectric films. A preliminary investigation of high-k dielectric device reliability suggests that a similar methodology can be adopted to project the reliability of scaled high-k films.

引用

页码：129 / 133

页数：5

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