A Memetic Algorithm based PVT Variation-aware Robust Transistor Sizing Scheme for Power-Delay Optimal Digital Standard Cell Design

Higher yield, climbing transistor counts and shrinking dimensions of a single Integrated Circuit (IC) have always been the demands in the fabrication market. However, this increased complexity and miniaturization of transistors present a challenge, due to high critical process variations combined with a ubiquitous presence of temperature and supply voltage variations, to achieve the required specification bounds on the desired performance of the circuits. Since optimization has become a very crucial task in IC design, the paper presents an efficient transistor sizing based optimization technique of the CMOS circuits to achieve low power, high performance and high yield design goals. The proposed memetic algorithm judiciously utilizes a threshold based local search procedure to improve convergence in its inherent genetic nature. The algorithm optimizes with the effect of temperature [-55 to 125]degrees C and supply voltage +/- 10% variations and in addition a number of statistically sampled sets generated as Gaussian, Latin Hypercube and Correlation Screened schemes of process variations. The proposed technique is applicable to any technology node and has been tested over several standard single-stage and some complex multi-stage digital circuits designed using a Multi-Gate high-K dielectric (MGK) 22nm CMOS model. The reduction in leakage power with propagation delay goes as high as 53% with 9% respectively, as observed across the various digital circuits.