共 28 条
[1]
VHDL implementation of fast NxN multiplier based on vedic mathematic
[J].
2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3,
2007,
:472-475
[2]
[Anonymous], 1968, Computer approximations
[3]
[Anonymous], 2008, PROC INT SOC DESIGN, DOI DOI 10.1109/SOCDC.2008.4815685
[4]
Avizienis A., 1961, IRE Transactions on Electronic Computers, P389
[5]
Bi SQ, 2005, FIFTH INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, PROCEEDINGS, P396
[6]
Booth A. D., 1952, Q J MECH APPL MATH, VIV, P236
[7]
CARBOGNANI F, 2005, P MID W S CIRC SYST, P1406
[8]
Improved multiplier of CSD used in digital signal processing
[J].
PROCEEDINGS OF 2008 INTERNATIONAL CONFERENCE ON MACHINE LEARNING AND CYBERNETICS, VOLS 1-7,
2008,
:2905-2908
[9]
Chung-Hsun Huang, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), P88, DOI 10.1109/ISCAS.2001.922177
[10]
Deschamps J.P., 2006, SYNTHESIS ARITHMETIC, P180