Optimal FPGA module placement with temporal precedence constraints

被引：78

作者：

Fekete, SP ^{[1
]}

Köhler, E ^{[1
]}

Teich, J ^{[1
]}

机构：

[1] Tech Univ Berlin, Dept Math, Berlin, Germany

来源：

DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/DATE.2001.915093

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

We consider the optimal placement of hardware modules in space and time for FPGA architectures with reconfiguration capabilities, where modules are modeled as three-dimensional boxes in space and time. Using a graph-theoretic characterization of feasible packings, we are able to solve the following problems: (a) Find the minimal execution rime of the given problem on an FPGA of fixed size. (b) Find the FPGA of minimal size to accomplish the tasks within a fixed rime limit. Furthermore, our approach is perfectly suited for the treatment of precedence constraints for the sequence of tasks, M which are present in virtually all practical instances. Additional mathematical structures are developed that lead to a powerful framework for computing optimal solutions. The usefulness is illustrated by computational results.

引用

页码：658 / 665

页数：8