An Efficient Processing Element Architecture for Pairwise Sequence Alignment

被引:0
作者
Isa, M. N. [1 ]
Murad, S. A. Z. [1 ]
Ismail, R. C. [1 ]
Ahmad, M. I. [2 ]
Jambek, A. B. [1 ]
Kamil, M. K. Md [1 ]
机构
[1] Univ Malaysia Perlis, Sch Microelect Engn, Pauh Putra, Perlis, Malaysia
[2] Univ Malaysia Perlis, Sch Comp & Commun Engn, Pauh Putra, Perlis, Malaysia
来源
2014 2ND INTERNATIONAL CONFERENCE ON ELECTRONIC DESIGN (ICED) | 2014年
关键词
component; FPGA; systolic arrays; Verilog HDL; pairwise sequence alignment; DNA; protein and SSEARCH 35;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
One of the most challenging tasks in sequence alignment is its repetitive and time-consuming alignment matrix computations. Alignment matrix scores are crucial for identifying regions of homology between biological sequences. In this paper, a parametrizable and area efficient processing element (PE) architecture for performing biological sequence alignment task especially for pairwise biological sequence alignment is designed. Its corresponding PE architecture realization was prototyped on Xilinx FPGA platform. FPGA has been chosen as it able to realize an array of systolic array-based PEs. Execution of the proposed parameterizable PE architecture have been conducted and comparison results have shown that the systolic arrays with parameterizable PE has gained at least 15x speed-up as compared to the well-known SSEARCH 35 solution.
引用
收藏
页码:461 / 464
页数:4
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