TCAD Based Study of a Novel 24 nm Quantum Well Symmetric IDG NMOS Transistor with ultra-low Ioff

This paper presents the design of a 24 nm symmetric Hetero Channel Si Independent Double Gate (IDG) NMOS transistor with Ge/Si/Ge channel structure (forming a Quantum Well in lateral direction), with elevated Si S/D Structure (also called Raised and Digged S/D Structure), n(+) polysilicon as front and back gate material (Buried Back Gate Structure), High-K Si3N4 spacer in order to suppress SCE's. The dc parameters of the device such as I-on, I-off, I-on/I-off ratio, subthreshold swing were evaluated for different back gate biasing and I-off and subthreshold swing were found to be optimum at back gate biasing of -0.6 V. The effect different front gate metals was also evaluated using TCAD simulations and it is observed that Molybdenum serves as an excellent front gate metal with extremely low I-off similar to 2 pA/mu m at back gate biasing of -0.6 V and subthreshold swing of similar to 135 mV/decade at back gate biasing of 0 V, with quite low I-on similar to 5x10(-7) A/mu m. To improve the on current an undoped channel structure is incorporated with the proposed QW IDG NMOS device, with a slight degradation of I-off as well as subthreshold swing. The on current is further enhanced by modulating the width of Si-QW in the channel, and it is found that Si-QW of width 11 nm provides optimum dc performance with I-on similar to 2.02x10(-5) A/mu m, I-off similar to 0.89243 pA/mu m and a subthreshold swing of similar to 108 mV/decade for the back gate biasing voltage of -0.8 V.