Three-dimensional integration scheme with a thermal budget below 300°C

A solution for the wiring problem in highly complex and embedded systems is the technology of three-dimensional integration. This approach allows a high interconnect density between two or more chips with very short signal or power lines. With the chip stacking concept shown here, a via density of up to 4400 vias per mm(2) is obtained for a chip thickness of 10 mu m. However, in this technology it seems also important to implement already fully processed CMOS and memory circuits and thus only frontend and backend processes are considered. This limits the maximum processing temperature to 300 degrees C to avoid any degeneration in pre-processed circuits. First results show very low leakage currents as well as very low through resistances. (c) 2007 Elsevier B.V All rights reserved.