The first IA-64 microprocessor

被引：48

作者：

Rusu, S ^{[1
]}

Singer, G ^{[1
]}

机构：

[1] Intel Corp, Santa Clara, CA 95052 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2000年 / 35卷 / 11期

关键词：

clock deskew; design for test; explicitly parallel instruction computing; IA-64; I/O compensation; microprocessor; source-synchronous bus;

D O I：

10.1109/4.881197

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The first implementation of the IA-64 architecture achieves high performance by using a highly parallel execution core, while maintaining binary compatibility with the IA-32 instruction set, Explicitly parallel instruction computing (EPIC) design maximizes performance through hardware and software synergy, The processor contains 25.4 million transistors and operates at 800 MHz. The chip is fabricated in a 0.18-mum CMOS process with six metal layers and packaged in a 1012-pad organic land grid array using C4 (flip-chip) assembly technology. A core speed back-side bus connects the processor to a 4-MB L3 cache.

引用

页码：1539 / 1544

页数：6

共 6 条

[1]

Ghani T., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P415, DOI 10.1109/IEDM.1999.824182

[2] Skew-tolerant domino circuits [J].