A unified approach to object-oriented VHDL

Abs and reuse are keys to dealing with the increasing complexity of electronic systems. We apply object-oriented modeling to achieve more reuse and higher abstraction in hardware design. This requires an object-oriented hardware description language, preferably an extension of VHDL. Several variants of such OO-VHDL are currently being debated. We present our unified approach, Objective VHDL, which adds object-oriented features to the VHDL design entity as well as to the type system to provide maximum modeling power.