A comparative study of CMOS circuit design styles for low-power high-speed VLSI circuits

An important issue in the design of VLSI circuits is the choice of the basic circuit approach and topology for implementing various logic and arithmetic functions. In this paper, several static and dynamic CMOS circuit design styles are evaluated in terms of area, propagation delay and power dissipation. The different design styles are compared by performing detailed transistor-level simulations on a benchmark circuit using HSPICE, and analysing the results in a statistical way. Based on the results of our analysis, some of the trade-offs that are possible during the design phase in order to improve the circuit power-delay product are identified.