Hot-carrier-induced circuit degradation for 0.18 μm CMOS technology

被引：3

作者：

Li, W ^{[1
]}

Li, Q ^{[1
]}

Yuan, JS ^{[1
]}

McConkey, J ^{[1
]}

Chen, Y ^{[1
]}

Chetlur, S ^{[1
]}

Zhou, J ^{[1
]}

Oates, AS ^{[1
]}

机构：

[1] Univ Cent Florida, Chip Design & Reliabil Lab, Sch Elect Engn & Comp Sci, Orlando, FL 32816 USA

来源：

INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/ISQED.2001.915244

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Because the supply voltage is not proportional scaled with the device size, the further scaling down of CMOS devices is in turn accompanied with more and more severe hot-carrier reliability problems. Hot-carriers, the high energy carriers due to high electric field in the channel, are injected into the gate oxide or cause trapping states generation between Si and SiO2 interface, which is accumulated and cause long run reliability problems in devices and circuits. In this paper, we describe a systematic method to evaluate the circuit degradation due to hot-carrier stressing. First the substrate current and gate leakage current models are improved for more accuracy in predicting the lifetime of the devices and circuits. The hot-carrier stressing characterization is carried out for 0.18 mum technology. The circuit performance degradation is then evaluated using the parameters extracted from 0.18 mum technology for both digital logic circuits and RF circuits.

引用

页码：284 / 289

页数：6