Vacuum Reflow Process Optimization for Solder Void Size Reduction in Semiconductor Packaging Assembly

被引:6
作者
Yeo, Siang Miang [1 ]
Yow, Ho-Kwang [2 ]
Yeoh, Keat Hoe [2 ]
bin Ishak, Shahrul Haizal [1 ]
机构
[1] Amkor Technol Inc, Kuala Langat 42507, Malaysia
[2] Univ Tunku Abdul Rahman, Lee Kong Chian Fac Engn & Sci, Ctr Photon & Adv Mat Res, Dept Elect & Elect Engn, Kajang 43000, Selangor, Malaysia
来源
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY | 2022年 / 12卷 / 08期
关键词
Temperature distribution; Packaging; Manufacturing; Ovens; Optimization; Vacuum systems; Size measurement; Bond line thickness (BLT); packaging assembly; Pb95Sn5; process optimization; solder void size reduction; vacuum reflow; DIE-ATTACH; THERMAL-RESISTANCE; RELIABILITY; IMPEDANCE;
D O I
10.1109/TCPMT.2022.3189995
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
The undesirable impacts of solder void defects on the reliability of die packages have prompted stringent requirements on solder void size control in the semiconductor packaging industry. Vacuum reflow process using Pb95Sn5 solder was studied, where critical process parameters within temperature and pressure profiles were varied for enhanced solder void size reduction, in comparison to conventional reflow process. Higher reflow temperature profile, faster pressure pump-down rate, and longer vacuum dwell time above threshold levels are critical conditions required for consistently achieving minimum solder void sizes well below the industry criteria. Application of threshold conditions using large volume reflow oven with industrial settings has achieved the single and the total solder void size over die size well below the standard 2.5% and 5% requirements, respectively, with majority of the samples attained the single and the total solder void size over die size below 1% and 2%, respectively. Solder bond line thickness exhibited a significant influence on the solder void size reduction and thus needs to be administered appropriately during die packaging assembly to achieve the maximum solder void size reduction.
引用
收藏
页码:1410 / 1420
页数:11
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