2T 2:1 MUX based 1 Bit Full Adder Design

被引：0

作者：

Singh, Neeraj Kumar ^{[1
]}

Sharma, Purnima Kumari ^{[1
]}

机构：

[1] North Eastern Reg Inst Sci & Technol, Dept Elect & Commun Engn, Nirjuli 791109, Arunachal Prade, India

来源：

2014 INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND SIGNAL PROCESSING (ICCSP) | 2014年

关键词：

xor; mux; full adder; sum; carry; CMOS; LOGIC; CELL;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper puts forward a methodology for designing 1 bit full adder using a 2T mux. The 2T mux is combined in a specific manner to get a full adder with sum and carry output. The resulting 1 bit full adder is made up of 16 transistors. The simulation is done using Cadence Virtuoso Simulator using 180nm technology and 1.8V power supply. The results show the efficiency of the design.

引用

页数：3

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