Analytical Model of the Parasitic Bipolar Junction Transistor in Low-Doped Double-Gate FinFETs for Pass-Gate Circuits

被引:4
作者
Yi, Boram [1 ]
Lee, Chang-Yong [2 ]
Oh, Jin-Hwan [3 ]
Lee, Boung Jun [1 ]
Seo, Sungkyu [1 ]
Yang, Ji-Woon [1 ]
机构
[1] Korea Univ, Dept Elect & Informat Engn, Sejong 30019, South Korea
[2] Dongby HiTek, Technol Enabling Team, Bucheon 14519, South Korea
[3] Hyundai Heavy Ind, Dept LV Circuit Breaker, Ulsan 44032, South Korea
基金
新加坡国家研究基金会;
关键词
Compact modeling; double-gate (DG) MOSFETs; FinFETs; floating-body (FB); parasitic bipolar junction transistor (BJT); SOI MOSFETS; DG MOSFETS;
D O I
10.1109/TED.2016.2600625
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The transient parasitic bipolar effect in floating-body double-gate FinFETs with low-doped bodies is analytically modeled. The obtained analytical transient bipolar current and charge models have predictive power for various device structures. These models are applicable when the majority carrier concentration in accumulation conditions noticeably exceeds the body doping concentration. The physical insights obtained from the developed current model are used to analyze the transient bipolar current I-BJT(t) for different device structures. It is shown that the gate-body-source capacitive coupling is an important parameter in I-BJT(t) control.
引用
收藏
页码:3864 / 3868
页数:5
相关论文
共 17 条
[11]   An analytic potential model for symmetric and asymmetric DG MOSFETs [J].
Lu, HX ;
Taur, Y .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (05) :1161-1168
[12]   Simulation Analysis of Bipolar Amplification in Independent-Gate FinFET and Multi-Channel NWFET Submitted to Heavy-Ion Irradiation [J].
Munteanu, D. ;
Autran, J. L. .
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2012, 59 (06) :3249-3257
[13]   Low-voltage transient bipolar effect induced by dynamic floating-body charging in scaled PD/SOI MOSFET's [J].
Pelella, MM ;
Fossum, JG ;
Suh, DW ;
Krishnan, S ;
Jenkins, KA ;
Hargrove, MJ .
IEEE ELECTRON DEVICE LETTERS, 1996, 17 (05) :196-198
[14]  
Pelella MM, 1995, 1995 IEEE INTERNATIONAL SOI CONFERENCE PROCEEDINGS, P8, DOI 10.1109/SOI.1995.526434
[15]   A continuous, analytic drain-current model for DG MOSFETs [J].
Taur, Y ;
Liang, XP ;
Wang, W ;
Lu, HX .
IEEE ELECTRON DEVICE LETTERS, 2004, 25 (02) :107-109
[16]   PSP-SOI: An advanced surface potential based compact model of partially depleted SOI MOSFETs for circuit simulations [J].
Wu, W. ;
Li, X. ;
Gildenblat, G. ;
Workman, G. O. ;
Veeraraghavan, S. ;
McAndrew, C. C. ;
van Langevelde, R. ;
Smit, G. D. J. ;
Scholten, A. J. ;
Klaassen, D. B. M. ;
Watts, J. .
SOLID-STATE ELECTRONICS, 2009, 53 (01) :18-29
[17]   AVALANCHE-INDUCED DRAIN SOURCE BREAKDOWN IN SILICON-ON-INSULATOR N-MOSFETS [J].
YOUNG, KK ;
BURNS, JA .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1988, 35 (04) :426-431