Optimisation for improved short-channel performance of surrounding/cylindrical gate MOSFETs

被引：10

作者：

Kranti, A

Rashmi

Haldar, S

Gupta, RS

机构：

[1] Univ Delhi, Dept Elect Sci, Semicond Devices Res Lab, New Delhi 110021, India

[2] Univ Delhi, Motilal Nehru Coll, Dept Phys, New Delhi 110021, India

来源：

ELECTRONICS LETTERS | 2001年 / 37卷 / 08期

关键词：

Gates (transistor) - Integrated circuit layout - Mathematical models - Optimization - Poisson equation - Thin films - ULSI circuits;

D O I：

10.1049/el:20010340

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new technique is proposed to optimise the device parameters of a thin-film Fully depleted SGT MOSFET to minimise short-channel effects. Thr model offers new opportunities for realising future ULSI circuits with SGTs.

引用

页码：533 / 534

页数：2

共 5 条

[1] Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's [J].

Auth, CP ;

Plummer, JD .

IEEE ELECTRON DEVICE LETTERS, 1997, 18 (02) :74-76

[2]

Endoh T, 1997, IEICE T ELECTRON, VE80C, P911

[3] SHORT-CHANNEL MOST THRESHOLD VOLTAGE MODEL [J].

RATNAKUMAR, KN ;

MEINDL, JD .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1982, 17 (05) :937-948

[4] IMPACT OF SURROUNDING GATE TRANSISTOR (SGT) FOR ULTRA-HIGH-DENSITY LSIS [J].

TAKATO, H ;

SUNOUCHI, K ;

OKABE, N ;

NITAYAMA, A ;

HIEDA, K ;

HORIGUCHI, F ;

MASUOKA, F .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1991, 38 (03) :573-578

[5] SCALING THE SI MOSFET - FROM BULK TO SOI TO BULK [J].

YAN, RH ;

OURMAZD, A ;

LEE, KF .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1992, 39 (07) :1704-1710

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