A 70.8 dB 0.0045 mm2 Low-power Continuous-Time Incremental Delta-Sigma Modulator for Multi-Site Neural Recording Interfaces

The implementation of implantable multi-site neural recording systems is a very challenging task for which area-efficient low-power pre-amplifiers and analog-to-digital converters (ADCs) are needed. For such applications, the design and implementation of an area-and power-optimized continuous-time incremental Delta-Sigma ADC are presented in this paper. The second-order continuous-time modulator features an active RC-integrator based loop-filter of type cascade-of-integrators-with-distributed-feedback with area-optimized passive components. The ADC is implemented in a 0.18 mu m CMOS process and achieves a signal-to-noise-and-distortion ratio of 70.8 dB in a bandwidth of 10 kHz. It occupies an area of 0.0045 mm(2) and consumes a power of 16.6 mu W whereby the Schreier figure-of-merit results in 165.4 dB.