Timing Speculation-Aware Instruction Set Extension for Resource-Constrained Embedded Systems

Performance, area, and power are important issues for many embedded systems. One area-and power-efficient way to improve performance is instruction set architecture (ISA) extension. Although existing works have introduced applicationspecific accelerators co-operating with a basic processor, most of them are still not suitable for embedded systems with stringent resource and/or power constraints because of excess, powerhungry resources in the basic processor. In this paper, we propose ISA extension for such stringently constrained embedded systems. Contrary to previous works, our work rather simplifies the basic processor by replacing original power-hungry resources with power-efficient alternatives. Then, considering the application features (not only input patterns but also instruction sequence), we extend software binary with new instructions executable on the simplified processor. These hardware and software extensions can jointly work well for timing speculation (TS). To the best of our knowledge, this is the first TS-aware ISA extension applicable to embedded systems with stringent area-and/or power-constraints. In our evaluation, we achieved 29.9% speedup in execution time and 1.5x aggressive clock scaling along with 8.7% and 48.3% reduction in circuit area and power-delay product, respectively, compared with the traditional worst-case design.