Low-noise SOI Hall devices

被引：6

作者：

Haddab, Y ^{[1
]}

Mosser, V ^{[1
]}

Lysowec, A ^{[1
]}

Suski, J ^{[1
]}

Demeûs, L ^{[1
]}

Renaux, C ^{[1
]}

Adriaensen, S ^{[1
]}

Flandre, D ^{[1
]}

机构：

[1] Wavecom SA, F-92442 Issy Les Moulineaux, France

来源：

NOISE AND INFORMATION IN NANOELECTRONICS, SENSORS AND STANDARDS | 2003年 / 5115卷

关键词：

low-frequency noise; Hall effect; sensors; SOI technology; noise reduction; shape effect; Hall cross; LOCOS; 2D conduction;

D O I：

10.1117/12.490185

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Hall sensors are used in a very wide range of applications. A very demanding one is electrical current measurement for metering purposes. In addition to high precision and stability, a sufficiently low noise level is required. Cost reduction through sensor integration with low-voltage/low-power electronics is also desirable. The purpose of this work is to investigate the possible use of SOI (Silicon On Insulator) technology for this integration. We have fabricated SOI Hall devices exploring a wide range of silicon layer thickness and doping level. We show that noise is influenced by the presence of LOCOS and p-n depletion zones near the edges of the active zones of the devices. A proper choice of SOI technological parameters and process flow leads to up to 18 dB reduction in Hall sensor noise level. This result can be extended to many categories of devices fabricated using SOI technology.

引用

页码：196 / 203

页数：8

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